1. Field of the Invention
The present invention relates to a semiconductor memory device equipped with a memory transistor including a floating gate and a control gate and a peripheral transistor for controlling the memory transistor, and to a method of manufacturing the particular semiconductor memory device.
2. Description of the Related Art
A NAND type flash memory, which is a kind of nonvolatile memory, comprises a memory transistor in which a floating gate and a control gate are laminated one upon the other and a peripheral transistor is arranged to surround the periphery of the memory transistor. In many cases, the gate of the peripheral transistor is formed by using an electrode material equal to that of the floating gate of the memory transistor. The method of manufacturing the particular flash memory will now be described briefly with reference to the accompanying drawings.
FIGS. 58A, 58B to 66A, 66B are cross sectional views collectively showing a conventional method of manufacturing a semiconductor memory device. FIGS. 58A to 66A are cross sectional views perpendicular to the element separating region included in the memory cell region. On the other hand, FIGS. 58B to 66B are cross sectional views perpendicular to the gate electrode in the memory cell region.
In the first step, a first insulating film 12 forming a gate insulating film is formed on a semiconductor substrate (silicon substrate) 11, followed by forming a first electrode material layer 13 on the first insulating layer 12, as shown in FIGS. 58A and 58B. The first electrode material layer 13 is formed of a polycrystalline silicon (polysilicon) into which an impurity is not introduced. Then, a second insulating film 14 is formed on the first electrode material layer 13, followed by forming an element separating region of an STI (Shallow Trench Isolation) structure consisting of an element separating insulating film 15 such that the element separating insulating film 15 extends through the second insulating film 14, the first electrode material layer 13, and the first insulating film 12 into the semiconductor substrate 11.
In the next step, the element separating insulating film 15 is partly etched such that the upper surface of the element separating insulating film 15 is positioned lower than the upper surface of the first electrode material layer 13, followed by peeling off the second insulating film 14, as shown in FIGS. 59A and 59B.
Then, a resist layer 16a is formed on the first electrode material layer 13 in the PMOS region, as shown in FIGS. 60A and 60B. After formation of the resist layer 16a, ion implantation using, for example, phosphorus ions, is applied to the first electrode material layer 13 in the memory cell region with the resist layer 16a used as a mask, followed by applying anneal to the ion-implanted region so as to form N+-type first conductive layers 13a, 13b. Incidentally, the reference numeral 13a shown in FIGS. 60A, 60B denotes the first conductive layer in the memory cell region, and the reference numeral 13b shown in FIGS. 60A, 60B denotes the first conductive layer in the NMOS region. It should also be noted that the first conductive layer 13a in the memory cell region performs the function of the floating gate of the memory transistor. After formation of the N+-type first conductive layers 13a, 13b, the resist layer 16a is removed.
In the next step, a resist layer 16b is formed on the first conductive layers 13a, 13b as shown in FIGS. 61A, 61B. After formation of the resist layer 16b, ion implantation using, for example, boron ions is applied to the first electrode material layer 13 in the PMOS region, followed by applying annealing to the ion-implanted region so as to form a P+-type first conductive layer 13c. After formation of the P+-first conductive layer 13c, the resist layer 16b is removed.
Then, a third insulating film 17 is deposited over the first conductive layers 13a, 13b, 13c and the element separating insulating film 15, as shown in FIGS. 62A and 62B, followed by depositing a second electrode material layer 18 on the third insulating film 17. It should be noted that the second electrode material layer 18 is formed of polysilicon into which an impurity is not introduced.
In the next step, a resist layer 19 is formed on the second electrode material layer 18, followed by patterning the resist layer 19, as shown in FIGS. 63A, 63B. The patterned resist layer 19 is used as a mask in the next step for removing the second electrode material layer 18, the insulating film 17 and the first conductive layers 13a, 13b, 13c, thereby forming the gate patterns of the memory transistor and the peripheral transistor. Then, the resist layer 19 is removed, followed by a post-oxidation treatment.
Then, an insulating film 22 is formed on the side surface of the gate of the peripheral transistor, as shown in FIGS. 64A, 64B, followed by forming a resist layer 23 on the first insulating film 12 and the second electrode material layer 18 included in the PMOS region. The resist layer 23 thus formed is used as a mask in the subsequent step for introducing, for example, arsenic (As) ions as an impurity by means of ion implantation, followed by diffusing the introduced impurity by annealing. As a result, a second conductive layer 18a forming the control gate of the memory transistor and N+-type source/drain diffusion layers 21 are formed in the memory cell region. On the other hand, a second conductive layer 18b and N+-type source/drain diffusion layers 24 are formed in the NMOS region. Then, the resist layer 23 is removed.
In the next step, a resist layer 25 is formed on the first insulating film 12 and the second conductive layers 18a, 18b in the memory cell region and the NMOS region. After formation of the resist layer 25, ion implantation is performed by using, for example, boron ions as an impurity, followed by applying annealing to the ion-implanted region so as to diffuse the implanted boron ions. As a result, a second conductive layer 18c and P+-type source/drain layers 26 are formed in the PMOS region. Then, the resist layer 25 is removed.
After removal of the resist layer 25, the first insulating layer 12 is removed so as to expose the source/drain diffusion layers 21, 24 and 26 to the outside, as shown in FIGS. 66A and 66B. Then, salicide (Self Aligned Silicide) films 27a, 27b, 27c, 27d consisting of a metal having a high melting point are formed on the second conductive layers 18a, 18b, 18c and the source/drain diffusion layers 21, 24, 26, respectively. In this fashion, a memory transistor 28 is formed in the memory cell region, and an NMOS transistor 29 and a PMOS transistor 30 are formed in the peripheral circuit region.
In the memory cell region of the conventional semiconductor memory device described above, the salicide film 27a is formed on the control gate formed on the second conductive layer 18a, and the salicide film 27d is also formed on the source/drain diffusion layer 21.
However, if the salicide film 27d is formed on the source/drain diffusion 21 of the memory cell region, it is possible for the reliability of the device characteristics such as the data retention characteristics and the data program/erase endurance cycle characteristics to be reduced in the flash memory. Also, where the salicide film 27d is also formed on the source/drain diffusion layer 21 of the memory cell region, a serious problem is brought about that the degree of freedom in terms of the element design of the source-drain of the memory cell device is markedly limited in order to satisfy both the formation of the electrode material and the device operation.
It was customary to use CMOS transistors of a dual work function gate in a nonvolatile memory for a low power consumption and in a high performance transistor requiring a high operating speed. The CMOS transistors include a surface channel type NMOS transistor and a surface channel type PMOS transistor. For forming these transistors, an electrode material into which an impurity is not introduced is deposited first. Then, arsenic (As) ions or phosphorus (P) ions, which are N-type impurities, are introduced by means of ion implantation into the gate region of the NMOS transistor, and boron (B) ions, which are P-type impurities, are introduced by means of ion implantation into the gate region of the PMOS transistor. What should be noted is that the gate electrode of the dual work function gate structure was formed in the past by separately implanting P-type and N-type impurities by light exposure technology with the N-type gate electrode and the P-type electrode used as masks. However, the conventional method of forming a gate electrode of the dual work function gate structure requires a large number of process steps and each process step is complex, leading to an increased manufacturing cost of the semiconductor memory device.